1. What changed

The headline change is the width of the road, not the speed limit. Under JESD270-4, HBM4 doubles the I/O count from 1,024 to 2,048 and independent channels from 16 to 32. Per-stack bandwidth therefore roughly doubles without pushing per-pin speed to a difficult place — a deliberate choice, because signal integrity and power both degrade quickly as pin rates climb.

The second change is less visible and matters more for the industry's structure. The base die that sits underneath the stack and manages data flow moves from a memory process to a foundry logic process. That allows far more capable control circuitry, and it makes memory vendors dependent on foundry partners for a component they previously made themselves. The boundary between memory manufacturing and logic manufacturing is now blurred in a way it was not two generations ago.

2. The numbers

JEDEC sets the standard pin rate at 8Gbps, which yields roughly 2TB/s per stack. SK hynix has stated it achieved operation above 10Gbps; a straight conversion puts that near 2.5TB/s, though no supplier publishes a throughput figure at that speed. Against HBM3E 12-high — 36GB at roughly 1.2TB/s — the per-stack gap is close to a doubling, and suppliers cite power efficiency gains above 40% versus the prior generation.

That gap is the whole argument for the generation. An accelerator's usable throughput is bounded by how fast it can be fed, not by how fast it can multiply — a large language model reads its entire parameter set from memory for each token it produces. Doubling bandwidth per stack moves the ceiling directly. Higher stacks and a logic base die do raise unit cost, and market researchers broadly expect HBM4 to price above HBM3E, but no supplier has published a number.

3. What is still open

Several things commonly reported as settled are not. The 12nm-class foundry process said to be used for SK hynix's base die has not been confirmed by the manufacturer. Pricing is entirely unpublished. The timing for 16-high 64GB parts — allowed by the spec but not yet in volume — remains unannounced, as does the schedule for HBM4E, for which samples have shipped against a 2027 production target.

Heat is the constraint least discussed and most likely to bind. Stacking higher and clocking faster raises total dissipation even as efficiency per bit improves, and cooling design increasingly decides which parts a customer can actually deploy. SK hynix has said it is developing an approach it calls iHBM that lowers thermal resistance by more than 30%; nothing comparable has been detailed publicly by its competitors.