What the reticle limit is — the 26×33mm ceiling stopping AI chips from growing
The reticle limit is the largest area a lithography scanner can print onto a wafer in a single exposure. On conventional EUV tools that field measures 26 by 33 millimetres, about 858 square millimetres, and it acts as a physical ceiling on how large a single chip can be. The limit has grown more consequential each year because AI accelerators keep expanding toward it. High-NA EUV, the next generation of tool, draws finer patterns but halves the printable area to roughly 26 by 16.5 millimetres, which forces designers to split one die across two exposures and join them — a technique called stitching. Data Intel presented at the SPIE conference shows that stitching cuts a High-NA scanner's throughput from about 175 wafers per hour to about 125, a loss of nearly 30 percent. That is why Intel has spent more than three years championing a larger 6-by-12-inch mask format, and why reports on September 8, 2026 said TSMC, Samsung and Intel now all support a 12-inch photomask standard. In the same week Intel and ASML said they had processed more than one million wafers using High-NA EUV
The three lines
- Definition — the largest area printed in a single exposure. On EUV that is 26×33mm (~858mm²), a ceiling on chip size
- Problem — High-NA EUV gains resolution but halves the field to ~26×16.5mm, forcing two exposures stitched together
- Cost — stitching drops throughput from ~175 to ~125 wafers an hour, about 30 percent, hence the 12-inch mask push
Key questions
- What does the reticle limit mean
- **It is the size of the stamp you can press once.** Chips are made by printing circuit patterns onto a wafer with light. The pattern master is called a **reticle** or **photomask**, and the image it forms on the wafer is the **exposure field**. | Tool | Exposure field | Area | |---|---|---| | Conventional EUV (NA 0.33) | **26 × 33 mm** | ~**858 mm²** | | High-NA EUV (NA 0.55) | ~**26 × 16.5 mm** | ~**429 mm²** | **That number is the maximum size of a single chip.** A die larger than 858 mm² cannot be printed in one go, which is why discussions of large AI accelerators keep returning to the phrase **'approaching the reticle limit.'** **A common misreading is worth heading off.** The reticle limit is a **manufacturing** constraint, not a **design** one. Larger compute units can still be built — by joining chiplets in a package, by splitting one die across exposures (stitching), or by binding many chips at rack scale over an interconnect (「What Grace Blackwell NVL72 is」). **Each of those routes has a price attached.**
- Why does High-NA shrink the field
- **It is the cost of widening the lens angle to draw finer features.** NA, the numerical aperture, describes how wide an angle of light the optics gather. Higher NA resolves smaller features. Conventional EUV is 0.33; High-NA is 0.55. **Widening that angle changes the demagnification on one axis.** High-NA tools shift one axis from 4× to 8× reduction, so the image formed from the same-size mask is **halved in one direction.** That is the move from 26×33 to 26×16.5. | Item | Conventional EUV | High-NA EUV | |---|---|---| | Numerical aperture | 0.33 | **0.55** | | Resolution | baseline | **finer** | | Exposure field | 26 × 33 mm | **26 × 16.5 mm** | | To build a large chip | print it | **print twice and stitch** | **High-NA is therefore a trade, not a pure improvement.** It buys resolution and sells area. And because this is the era of ever-larger AI accelerators, **it happens to sell exactly the thing that is scarcest.**
- What does stitching actually cost
- **About 30 percent of throughput.** Intel's SPIE data shows that using today's 6-inch masks on a High-NA tool with stitching moves wafer output as follows. | Approach | Wafers per hour | |---|---| | Without stitching | ~**175** | | **With stitching** | ~**125** | | Loss | ~**29%** | **Lithography tools are the most expensive machines in a fab.** A High-NA EUV scanner is reported in the hundreds of millions of dollars. Cutting its throughput by 30 percent means **buying more machines to reach the same output** — more capital expenditure, more depreciation, and eventually more cost per chip. **The proposed fix is a bigger mask.** Intel has pushed a **6-by-12-inch mask format for more than three years**, and on September 8, 2026 reports said **TSMC, Samsung and Intel all now support a 12-inch photomask standard.** A larger mask prints a large die without stitching, and the 30 percent disappears. **Changing a mask standard is not changing one machine, though.** Mask blank manufacturing, mask inspection and repair tools, mask transport pods and fab automation are all built around 6-inch. **That is exactly why three competitors have to back it together.**
AI chips cannot grow because of the size of the stamp, not the ambition of the design. And the next-generation tool cuts that stamp in half.
1. One-sentence definition
The reticle limit is the largest area a lithography scanner can print onto a wafer in a single exposure.
| Tool generation | Exposure field | Area |
|---|---|---|
| Conventional EUV (NA 0.33) | 26 × 33 mm | ~858 mm² |
| High-NA EUV (NA 0.55) | ~26 × 16.5 mm | ~429 mm² |
A die larger than 858 mm² cannot be printed in one pass. Hence the recurring phrase in large-accelerator coverage: approaching the reticle limit.
2. The next generation is narrower
NA describes the angle of light the optics gather; higher NA resolves finer features. But widening that angle shifts one axis from 4× to 8× demagnification, halving the image in that direction.
| Item | Conventional EUV | High-NA EUV |
|---|---|---|
| Numerical aperture | 0.33 | 0.55 |
| Resolution | baseline | finer |
| Exposure field | 26 × 33 mm | 26 × 16.5 mm |
| Building a large chip | print it | print twice, stitch |
High-NA is a trade rather than an improvement. It buys resolution and sells area — in an era when area is the scarce good.
3. The price of stitching — 30 percent of throughput
Printing a die in two passes and joining them is called stitching. Intel's SPIE data:
| Approach | Wafers per hour |
|---|---|
| Without stitching | ~175 |
| With stitching | ~125 |
| Loss | ~29% |
A scanner is the most expensive machine in a fab. Cutting its throughput 30 percent means buying more of them for the same output, which raises capital expenditure and depreciation and eventually lands in the cost of the chip (「How long capex takes to reach chip prices」).
4. The fix is a larger mask — and it takes three companies to agree
Intel has championed a 6-by-12-inch mask format for more than three years. Reports on September 8, 2026 said TSMC, Samsung and Intel all now support a 12-inch photomask standard. A bigger mask prints a large die without stitching, and the 30 percent loss disappears.
But changing a mask standard is not changing one machine.
| What else must change | Why |
|---|---|
| Mask blank manufacturing | different substrate size |
| Mask inspection and repair tools | designed around 6-inch |
| Mask transport pods | fixed dimensions |
| Fab automation | handlers are sized to the pod |
That is exactly why three competitors have to back it together. A single company moving to 12-inch alone would have to build a supply chain by itself.
In the same week, Intel and ASML said they had processed more than one million wafers with High-NA EUV. That figure combines tool certification, testing, R&D and volume production on selected layers of Intel 18A (codename Panther Lake). It signals a move "from experiment to manufacturing" — it is not one million wafers of volume production.
5. What remains unresolved
- The 26×33mm and 26×16.5mm figures are industry-standard values, not quoted from this week's releases.
- The process and layer conditions behind 175→125 are unstated. Different conditions give a different loss.
- No joint statement from the three companies was located. The 12-inch backing is as reported.
- The one million wafers is a combined figure, not volume production alone.
- Other routes to large compute are advancing in parallel — chiplet packaging and rack-scale interconnect (「What Grace Blackwell NVL72 is」·「What comes after HBM」). The larger mask is one option among several.
Sources
- Intel Newsroom — Intel Foundry and ASML accelerate industry readiness for High-NA EUV
- Evertiq — Intel Foundry and ASML report High NA EUV production milestone
- TechTimes — TSMC, Samsung, and Intel back 12-inch photomask standard to end 30% High-NA EUV throughput loss
- SemiWiki — High-NA EUV moves from experiment to manufacturing
- Semiecosystem (Mark LaPedus) — Intel provides update on High NA EUV