What comes after HBM — Samsung stacks onto the GPU, SK bridges to NAND
At FMS 2026 Samsung showed zHBM, stacking memory vertically onto the GPU, while SK hynix put forward 3D-stacked DRAM and High Bandwidth Flash
The three lines
- Samsung unveiled zHBM and 400-plus-layer 10th-generation NAND at FMS 2026 in Santa Clara
- SK hynix led with 3D-stacked DRAM 'G0.5' and High Bandwidth Flash, publishing a first HBF specification with SanDisk
- Both target the same problem — AI compute stalling on memory bandwidth — from opposite directions
Key questions
- How is zHBM different from HBM
- Today's HBM sits beside the GPU as a stack of DRAM connected by short traces across an interposer. Samsung's zHBM stacks the memory vertically onto the GPU itself — up rather than sideways. Samsung says the approach delivers up to 8x per-GPU performance versus fifth-generation HBM, up to 3x better performance per watt, and thermal resistance reduced to 10–25%. These are company figures, not verified production results.
- What is SK hynix's HBF
- High Bandwidth Flash — the HBM idea applied to NAND instead of DRAM. NAND is slower than DRAM but far cheaper per gigabyte, and much of AI inference involves data that is loaded once and read repeatedly. SK hynix published a first HBF specification with SanDisk to coincide with the show, alongside 'G0.5', a 3D-stacked DRAM.
- Why is this happening now
- Because compute units increasingly sit idle waiting for data. When GPUs get faster but memory cannot feed them, performance is set by bandwidth rather than arithmetic. HBM solved that by stacking DRAM to widen the pipe, but layer counts, power and heat are approaching practical limits while model sizes keep growing. The successor architecture has to be chosen now, years before it ships.
The premise this page has returned to repeatedly — that AI's bottleneck is memory, not compute — is now the industry's working assumption. At FMS 2026 in Santa Clara this month, Samsung Electronics and SK hynix offered competing answers to it.
Samsung went up. SK went wide.
1. Samsung — put the memory on top of the GPU
Samsung showed next-generation high bandwidth memory called zHBM, along with 400-plus-layer 10th-generation NAND.
The idea behind zHBM is to delete the distance. Current HBM stands as a stack of DRAM beside the GPU, joined by short traces across an interposer. "Short" is still sideways, and that distance costs power and latency. zHBM stacks the memory vertically onto the GPU — directly above rather than alongside.
Samsung's stated figures against fifth-generation HBM: up to 8x per-GPU performance, up to 3x performance per watt, and thermal resistance at 10–25%. The last item is the interesting claim. Putting memory on top of a GPU is normally assumed to trap heat, and Samsung asserts the opposite. These are company numbers, not verified production data.
2. SK hynix — DRAM alone is not enough
SK hynix pushed two things: a 3D-stacked DRAM called G0.5 and High Bandwidth Flash (HBF).
HBF is the larger conceptual bet. If HBM is DRAM stacked to widen bandwidth, HBF does the same with NAND flash. NAND is slower but dramatically cheaper per gigabyte. Much of AI inference involves data — model weights above all — that is written once and read continuously, a pattern that may not require DRAM speed. If so, cheap NAND with an engineered wide pipe is the better economics.
SK hynix published a first HBF specification with SanDisk timed to the show's opening. Setting the specification first is the bigger move: whoever defines the format tends to define the supply chain that follows.
3. Two answers, side by side
| Samsung | SK hynix | |
|---|---|---|
| Lead technology | zHBM (GPU-memory 3D vertical stack) | HBF (high bandwidth NAND) + G0.5 (3D DRAM) |
| Approach | Remove the distance — stack upward | Change the material — extend into NAND |
| Claimed gain | Up to 8x per GPU vs HBM5 (company figure) | Bandwidth per unit of cost and capacity |
| Also shown | 400+ layer 10th-gen NAND | First HBF specification with SanDisk |
| Hardest problem | Heat, yield, co-design with GPU vendors | NAND endurance and latency; standard adoption |
| Production timing | Undisclosed | Undisclosed |
The last two rows are the honest summary: both have declared a direction, neither has said when silicon arrives.
4. Why the contest maps to earnings
Memory profits turn on who becomes the standard supplier for the next format. Each HBM generation has moved market share substantially, and those shifts show up directly in the two companies' results. Post-HBM is the next round of the same game.
For investors, though, announcements at this stage are statements of intent. The decision that matters is made by GPU vendors — Nvidia above all — choosing an architecture, and that choice becomes visible in long-term supply contracts rather than trade show booths. As this page has noted before, capital spending and technical announcements reach prices and earnings on a long delay.
5. What remains unverified
Every zHBM performance figure is Samsung's own, with no independent benchmark. Production timing and customer adoption are undisclosed for zHBM, G0.5 and HBF alike. HBF sits at first-specification stage, and formal standards adoption is undecided. Whether the two roadmaps actually collide — or divide by workload and coexist — cannot yet be judged.
The structure of HBM and the bandwidth bottleneck is in "HBM explained: why stacked memory is AI's bottleneck." The lag from fab investment to prices is in "How long semiconductor capex takes to reach prices." This page follows up when adoption contracts are confirmed.