What a 2nm process is — nothing on the chip is 2 nanometers, so why AI chips line up for it
A 2nm process is the name of a semiconductor manufacturing generation, not a measurement — no line on the chip is two nanometers wide, because node numbers stopped matching physical dimensions decades ago. What really changes at 2nm is the transistor: it moves from FinFET, where the gate wraps the channel on three sides, to gate-all-around (GAA) nanosheets wrapped on all four, cutting leakage and delivering more performance per watt. TSMC began N2 volume production in Q4 2025 and plans the improved N2P for the second half of 2026; Samsung makes SF2 and Intel makes 18A. Microsoft's Maia 300, unveiled October 12, 2026, uses N2P only for its compute chiplets.
The three lines
- Name — '2nm' is a generation label, not a dimension. The real change is the transistor: FinFET to GAA nanosheets
- Timeline — TSMC N2 volume production Q4 2025, N2P second half of 2026; Samsung SF2 ramping, SF2P 2026; Intel 18A in production
- AI chips — more compute per watt is the prize; costs push designs like Maia 300 to put only compute on 2nm and the rest on cheaper nodes
Key questions
- What is a 2nm process
- **A manufacturing-generation name. Nothing is literally 2nm wide; the key change is the GAA transistor.** | Item | Detail | |---|---| | Meaning | Generation label (closer to marketing) | | Real dimensions | Key pitches are tens of nanometers | | Key change | FinFET to gate-all-around (GAA) nanosheets | | Benefit | Less leakage; more performance and density per watt | | Examples | TSMC N2/N2P, Samsung SF2, Intel 18A |
- When did TSMC start 2nm mass production
- **N2 entered volume production in Q4 2025; N2P is scheduled for the second half of 2026.** | Node | Volume production | Note | |---|---|---| | N2 | Q4 2025 | TSMC's first GAA nanosheet node | | N2P | 2H 2026 | Performance and power gains over N2 | | A16 | Later | Backside power delivery (reported) |
- TSMC 2nm vs Samsung 2nm vs Intel 18A
- **All use GAA transistors; they differ on timing, yield and customers. Yields are mostly estimates.** | Item | TSMC N2 | Samsung SF2 | Intel 18A | |---|---|---|---| | Transistor | GAA nanosheet | GAA (MBCFET) | GAA (RibbonFET) + backside power | | Production | Q4 2025 | Ramping 2025-26 | In production (Panther Lake) | | Yield | 'Good,' per TSMC | Estimates from <40% to 50-60% | 60%+ reported | | Next | N2P (2H 2026) | SF2P (2026), SF2Z (2027) | — |
Don't look for two nanometers inside a 2nm chip. No line on the chip is 2nm wide. Node names roughly tracked transistor dimensions until the 1990s; since then they have become generation numbers, shrinking by about 0.7x each step. What makes 2nm matter is not the number but that it is the generation where the transistor changes shape.
Microsoft's Maia 300 AI chip, unveiled October 12, 2026, builds its compute section on TSMC's 2nm-class N2P. Here's why AI chips want 2nm — and why they use it for only part of the chip.
1. What actually changes at 2nm
| Generation | Transistor | Sides of channel wrapped by gate | Era |
|---|---|---|---|
| Planar | Gate on a flat channel | 1 | Through ~20nm-class |
| FinFET | Channel raised like a fin | 3 | 16/14nm to 3nm (TSMC) |
| GAA nanosheet | Stacked thin sheets as channel | All 4 | TSMC 2nm; Samsung from 3nm |
A transistor is a switch: the gate turns current through the channel on and off. As transistors shrink, current leaks even when "off." Wrapping the gate fully around the channel locks the switch more firmly, cutting leakage so chips run faster at the same power or use less power at the same speed. Designers can also vary nanosheet width to tune for performance or efficiency. It's the same direction as memory makers standing transistors upright for 4F² DRAM: going three-dimensional to get past a limit.
2. Who makes it, and when
| Company | Node | Status | Note |
|---|---|---|---|
| TSMC | N2 | Volume production since Q4 2025 | First GAA; yields described only as "good" |
| TSMC | N2P | Volume production scheduled 2H 2026 | Improved N2; Maia 300 compute chiplets |
| Samsung | SF2 | Ramping | Exynos 2600; yield estimates conflict |
| Samsung | SF2P / SF2Z | 2026 / 2027 | SF2Z adds backside power |
| Intel | 18A | In production | Panther Lake; 60%+ yield reported |
Yield — the share of usable chips per wafer — is the core of foundry competition, but companies rarely disclose it, so most numbers are industry estimates. Samsung adopted GAA first at 3nm, yet TSMC is widely seen as ahead in landing major customers.
3. Why AI chips want 2nm — and use it sparingly
| Reason | Detail |
|---|---|
| Power is the bottleneck | Data centers run short of electricity before chips; compute per watt wins (Maia 300's "tokens per megawatt") |
| Die size limits | A single die can't exceed what lithography can expose; more transistors per area is the only way up |
| Cost | Leading-edge wafers are expensive and early yields lower |
| Chiplets | Put compute on 2nm, memory control and I/O on cheaper nodes, then package together |
| Packaging bottleneck | Silicon interposer and CoWoS capacity are tight |
Maia 300 puts only its compute chiplets on N2P; Reuters says supporting silicon uses 3nm. Reassembling those pieces is the job of advanced packaging, which has become a bottleneck of its own.
4. Frequently asked questions
| Question | Answer |
|---|---|
| What comes after 2nm? | Names move to angstroms — TSMC A16 (1.6nm-class), Intel 14A |
| Will phones get 2nm chips? | Yes; smartphones and HPC/AI split early 2nm demand |
| How does it relate to Korean memory? | Different process, but each 2nm AI chip carries several HBM stacks, lifting memory demand |
| Is a 2nm chip automatically faster? | No; design, memory, packaging and software must all line up |
| What is backside power delivery? | Moving power wiring to the wafer's back to free space for signals — a next-generation key |
5. What remains unconfirmed
- Yields: None of TSMC, Samsung or Intel publish official yields.
- Prices: 2nm wafer prices are estimates only.
- N2P timing: Whether "2H 2026" volume production is on schedule can be checked at TSMC's third-quarter earnings.
- Maia 300 volume: The reported 300,000+ chip TSMC discussion (The Information, August) is unconfirmed by the companies.
Sources
- TechSpot — TSMC's 2nm N2 process officially enters volume production
- AnandTech — TSMC: Performance and Yields of 2nm on Track
- Notebookcheck — Samsung Foundry announces new SF2Z node with backside power delivery
- TechInsights — 2nm process comparison
- Official Microsoft Blog — Microsoft to expand Azure Maia system to multi-gigawatt deployments