What 4F² DRAM is — a third smaller memory cell, and why China's CXMT knocked SK hynix 3.4%
4F² DRAM stores each bit in a cell measuring two minimum feature sizes by two (4F²), instead of the 6F² cell used in mainstream DRAM as of 2026, shrinking cell area by roughly a third so more capacity fits on each wafer. Getting there requires standing the transistor upright, with a vertical channel wrapped by the gate. Samsung and SK hynix are both developing it. On October 12, 2026, Samsung fell 3.6% and SK hynix 3.4% after China's ChangXin Memory Technologies (CXMT) said at a Shanghai industry event over the weekend of October 10-11 that it had made key progress on a 4F² cell and aims to launch DDR5 server modules using it by the end of 2026. CXMT disclosed no specifications, yields or volumes.
The three lines
- Definition — a DRAM cell in 4F² (2x2 feature sizes) vs. the mainstream 6F²; about 33% less cell area, needs a vertical transistor
- Race — SK hynix showed a 4F² roadmap in 2025; Samsung reportedly targets 2028 for sub-10nm 4F². CXMT targets server DDR5 by end-2026
- Market — October 12, 2026: Samsung -3.6%, SK hynix -3.4%, Micron about -4%. CXMT gave no specs, yields or volumes
Key questions
- What is 4F2 DRAM
- **A DRAM cell layout using 4F² of area per bit, about a third smaller than today's 6F².** | Item | 6F² (mainstream) | 4F² (next-gen) | |---|---|---| | Cell footprint | 3F x 2F | 2F x 2F | | Transistor | Lying flat (saddle-fin) | Standing vertical | | Area | Baseline | ~33% smaller | | Difficulty | In volume production | Vertical transistors are hard to make |
- CXMT 4F2 announcement
- **CXMT claimed key progress on a 4F² cell using a vertical surrounding-gate transistor and targets server DDR5 modules by end-2026.** | Item | Detail | |---|---| | Speaker | CXMT President Cao Kanyu | | Where / when | Industry event in Shanghai, weekend of Oct. 10-11, 2026 | | Technology | Vertical surrounding-gate transistor; addresses current leakage | | Product | DDR5 RDIMM for servers | | Timing | By end of 2026 | | Not disclosed | Specs, launch date, yield, volume |
- Why did SK hynix and Micron stock fall October 12 2026
- **China's CXMT signaled a denser server-memory design, raising fears of future competition in the most profitable segment.** | Stock | Move | Price | |---|---|---| | Samsung Electronics | -3.6% | 252,500 won | | SK hynix | -3.4% | 1,624,000 won | | CXMT (China) | -3.1% | 49.42 yuan | | Micron (US) | about -4% | $984.28 | | Western Digital | about -2% | $389.04 |
The next battleground in DRAM is cell shape, not line width. For decades, chipmakers packed in more memory by shrinking circuit lines. With DRAM line widths now in the low teens of nanometers, further shrinking is extremely hard. So the industry is turning to a different lever: shrinking the area each cell occupies at the same line width, by moving from a 6F² to a 4F² layout.
That shift moved Korean stocks on October 12, 2026. After China's ChangXin Memory Technologies (CXMT) said it had made progress on 4F² cells, Samsung Electronics fell 3.6% and SK hynix 3.4%.
1. What 4F² means
| Term | Meaning |
|---|---|
| F | The minimum feature size a process can draw |
| 6F² | Each cell occupies 3F x 2F — the mainstream layout for well over a decade |
| 4F² | Each cell occupies 2F x 2F — the densest practical layout |
| Difference | About 33% less cell area at the same feature size |
| Real chips | Peripheral circuits mean die savings near 30% (Samsung reports) |
A DRAM cell is a capacitor that stores charge plus one transistor that switches it. In today's 6F² cells the transistor lies flat on the silicon. Shrinking to 4F² means eliminating that horizontal footprint, so the transistor stands up: the channel becomes a vertical pillar and the gate wraps around it. The industry calls this a vertical channel transistor (VCT); SK hynix calls it a vertical gate (VG); CXMT calls its version a vertical surrounding gate.
2. Who is where
| Company | What's public | Timing |
|---|---|---|
| SK hynix | At VLSI 2025, a roadmap applying 4F² vertical gate and 3D DRAM to sub-10nm nodes, combined with wafer bonding that puts circuitry under the cell array | No mass-production date |
| Samsung | Formed a dedicated 4F² team; tried and failed to commercialize 4F² about a decade ago | Reportedly targets sub-10nm 4F² by 2028 |
| CXMT | "Key progress" on 4F² with a vertical surrounding gate; says it solved current leakage | Server DDR5 RDIMM by end-2026 |
| Micron | No timeline in this coverage | — |
CXMT's schedule sounding ahead of Korea's leaders is what rattled markets. But CXMT gave no detailed specs or launch date, and analysts flagged supply capacity and customer qualification as hurdles. Server memory is bought in volume only after months of customer validation, so there are big gaps between announcing, shipping and supplying at scale.
3. Why stocks fell: it's server memory
| What markets saw | Detail |
|---|---|
| Target segment | Server DDR5 — where memory makers have the most pricing power |
| The boom | Micron's adjusted gross margin hit 87% last quarter, up from 45.7% a year earlier |
| Tight supply | Micron CEO: "in calendar year 27 as well as 2028, we see demand exceeding supply" |
| The worry | New entrants during booms have historically turned the cycle |
| The counterpoint | It's still a target; AI demand is absorbing all output so far |
In Seoul, Samsung fell to 252,500 won (-3.6%) and SK hynix to 1,624,000 won (-3.4%); in New York, Micron dropped about 4% to around $984.28. CXMT itself slipped 3.1% in China. Korean exports are at records — chips rose 170.9% in October 1-10 — but worries about the next cycle are one reason stocks and trade data are diverging.
4. Frequently asked questions
| Question | Answer |
|---|---|
| Is 4F² the same as 3D DRAM? | No. 4F² packs cells more tightly in a plane; 3D DRAM stacks cells in layers. 4F² is seen as a step toward 3D |
| How does it relate to HBM? | HBM stacks DRAM dies; denser dies mean more capacity per HBM stack |
| Does NAND work this way? | NAND already stacks cells hundreds of layers high; DRAM's capacitors make stacking harder |
| When will PC memory change? | Servers are the likely first use; no consumer timeline has been given |
5. What remains unconfirmed
- CXMT hardware: Whether server DDR5 actually ships by end-2026, and at what yield and volume.
- Korean timelines: Samsung's 2028 target is reported; SK hynix hasn't named a date.
- Export controls: How US curbs on chip equipment to China affect CXMT's 4F² ramp was not addressed.
- Closing prices: Korean share moves are intraday-report figures.
Sources
- Investing.com — Samsung, SK Hynix shares drop as China's CXMT flags progress in memory development
- 24/7 Wall St. — Memory Stocks Slide as China's CXMT Flags Denser Chip Design
- Invezz — Why are Micron, SK Hynix stocks falling on Monday?
- StorageNewsletter — IEEE VLSI 2025: SK hynix presents future DRAM technology roadmap
- TheElec — Samsung forms team to develop 4F2 DRAM